Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 11/10/2023
Document Table of Contents

5.3.8. CvP Programming Control Register

Table 12.  CvP Programming Control Register (Byte Offset: 0xBAC)
Bits Name Reset Value Access Description
[31:2] 0x0000 RO Reserved.
[1] START_XFER 1'b0 RW Sets the CvP output to the FPGA control block indicating the start of a transfer.
[0] CVP_CONFIG 1'b0 RW When set to 1, the FPGA control block begins a transfer via CvP.