Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 12/19/2022
Document Table of Contents

6.2.1. Instantiating the PCIe* Hard IP

Follow the steps from Generating the Synthesis HDL files for Avalon -ST Intel Stratix 10 Hard IP for PCI Express section to instantiate PCIe* Hard IP and generate the synthesis HDL files with CvP enabled.

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