- 6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express
1.3. CvP Modes
The CvP configuration scheme supports the following modes:
- CvP Initialization mode
- CvP Update mode
CvP Initialization Mode
This mode configures the CvP PCIe* core using the peripheral image of the FPGA through the on-board configuration device. Subsequently, configures the core fabric and all GPIOs through PCIe* link.
Benefits of using CvP Initialization mode include:
- Satisfying the PCIe* wake-up time requirement
- Saving cost by storing the core image in the host memory
CvP Update Mode
The CvP update mode is available after the FPGA enters user mode. You can configure the device through full chip configuration or CvP initialization initially to bring the device into user mode. In user mode, the PCIe* link is available for normal PCIe* applications as well as to perform an FPGA core image update.
The CvP update mode uses the same process as root partition reuse in block-based design, which allows you to reuse the device periphery.
Choose this mode if you want to update the core image for any of the following reasons:
- To change core algorithms logic blocks
- To perform standard updates as part of a release process
- To customize core processing for different components that are part of a complex system
|Supported Tile||PCIe* Version||Supported CvP Modes|
|H- and L-tile||PCIe* 1.0/ PCIe* 2.0 / PCIe* 3.0||CvP Initialization, CvP Update|
PCIe* 1.0/ PCIe* 2.0 / PCIe* 3.0 / PCIe* 4.0
PCIe* 4.0 x16
PCIe* 3.0 x16
PCIe* 3.0 1x8
PCIe* 4.0 1x8
PCIe* 3.0 2x8
PCIe* 4.0 2x8
Note: You can only select PCIe* 3.0 and above in the PCIe* Hard IP, but the host can down-train the link to PCIe* 1.0 and PCIe* 2.0 if necessary.
CvP Limitations and Restrictions
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