Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 11/10/2023
Document Table of Contents Modifying MSEL/DIP switch on Intel® Stratix® 10 FPGA Development Kit

The MSEL/DIP switch labeled SW1 at the front part of the Intel® Stratix® 10 FPGA Development Kit. Select Active Serial x4 (Fast mode) for CvP operation.
Table 14.  MSEL Pin Settings for Each Configuration Scheme of Intel® Stratix® 10 Devices
Configuration Scheme MSEL[2:0]
AS (Fast mode - for CvP)6 001
6 To support AS fast mode, the VCCIO_SDM of Intel® Stratix® 10 device must be fully ramped-up within 10ms to the recommended operating conditions. The delay between the device exiting POR and the SDM Boot-up is shorter for the fast mode compared to the normal mode. Therefore, AS fast mode is the recommended configuration scheme for CvP because the device can conform to 120 ms of power stable to PCIe* link active time.