Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 4/01/2024
Document Table of Contents

POR Specifications

Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration.

Table 86.  POR Delay Specification For specification status, see the Data Sheet Status table
POR Delay Minimum Maximum Unit
AS (Normal mode), AVST ×8, AVST ×16, AVST ×32 11.5 20.2 ms
AS (Fast mode) 1.5 7.6 ms