Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 4/01/2024
Document Table of Contents

AS Configuration Timing

Table 89.  AS Timing Parameters

Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. Refer to the related information to calculate the maximum allowable skew tolerance for nCSO and AS_DATA pins to AS_CLK.

For specification status, see the Data Sheet Status table

Symbol Description Minimum Typical Maximum Unit
Tclk 131 AS_CLK clock period 6.02 ns
Tdutycycle AS_CLK duty cycle 45 50 55 %
Tdcsfrs AS_nCSO[3:0] asserted to first AS_CLK edge 8.5132 ns
Tdcslst Last AS_CLK edge to AS_nCSO[3:0] deasserted 6.8132 ns
Tdo 133 AS_DATA[3:0] output delay –0.6 0.6 ns
Text_delay 134 135 Total external propagation delay on AS signals 0 13.5 ns
Tdcsb2b Minimum delay of slave select deassertion between two back-to-back transfers 62 ns
Figure 28. AS Configuration Serial Output Timing Diagram
Figure 29. AS Configuration Serial Input Timing Diagram
131 AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash setup/hold time specifications and AS timing specifications in this data sheet. For AS using multiple serial flash devices, refer to the related information for the recommended AS_CLK frequency and maximum board loading.
132 AS operating at maximum clock frequency = 166 MHz. The delay is larger when operating at AS clock frequency lower than 166 MHz.
133 Load capacitance for DCLK = 12 pF and AS_DATA = 27 pF. Intel recommends obtaining the Tdo for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash setup time,
  • Tsu = Tclk/2 - Tdo(max) + Tbd_clk – Tbd_data(max)
  • Tho = Tclk/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
134 Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
  • Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
  • Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.
  • Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
  • Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
135 Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency. For more details, refer to the related information.