Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 7/13/2023
Public
Document Table of Contents
Document Table of Contents x
Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: M-Series
Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC)
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: M-Series

AS Configuration Timing

Table 89.  AS Timing Parameters

Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. Refer to the related information to calculate the maximum allowable skew tolerance for nCSO and AS_DATA pins to AS_CLK.

For specification status, see the Data Sheet Status table

Symbol Description Minimum Typical Maximum Unit
Tclk 127 AS_CLK clock period — 6.02 — ns
Tdutycycle AS_CLK duty cycle 45 50 55 %
Tdcsfrs AS_nCSO[3:0] asserted to first AS_CLK edge 8.5128 — — ns
Tdcslst Last AS_CLK edge to AS_nCSO[3:0] deasserted 6.8128 — — ns
Tdo 129 AS_DATA[3:0] output delay –0.6 — 0.6 ns
Text_delay 130 131 Total external propagation delay on AS signals 0 — 13.5 ns
Tdcsb2b Minimum delay of slave select deassertion between two back-to-back transfers 62 — — ns
Figure 27. AS Configuration Serial Output Timing Diagram
Figure 28. AS Configuration Serial Input Timing Diagram
Related Information
127 AS_CLK fMAX has dependency on the maximum board loading. For AS single device configuration or AS using multiple serial flash devices configuration, use the equations in Tdo and Text_delay notes to ensure your board has sufficient timing margin to meet flash setup/hold time specifications and AS timing specifications in this data sheet. For AS using multiple serial flash devices, refer to the related information for the recommended AS_CLK frequency and maximum board loading.
128 AS operating at maximum clock frequency = 166 MHz. The delay is larger when operating at AS clock frequency lower than 166 MHz.
129 Load capacitance for DCLK = 12 pF and AS_DATA = 27 pF. Intel recommends obtaining the Tdo for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPIC simulation. To analyze flash setup time,
  • Tsu = Tclk/2 - Tdo(max) + Tbd_clk – Tbd_data(max)
  • Tho = Tclk/2 + Tdo(min) – Tbd_clk + Tbd_data(min)
130 Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
  • Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
  • Tco: Output hold time and clock low to output valid of flash device. This delay must be used to ensure Text_delay is within the minimum and maximum specification values.
  • Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
  • Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
131 Text_delay specification is based on AS_CLK = 166 MHz. The value can be larger at lower AS_CLK frequency. For more details, refer to the related information.
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