Visible to Intel only — GUID: doq1657772388165
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: doq1657772388165
Ixiasoft
Avalon® Streaming Configuration Timing
Symbol | Description | Minimum | Unit |
---|---|---|---|
tACLKH | AVST_CLK high time | 3.6 | ns |
tACLKL | AVST_CLK low time | 3.6 | ns |
tACLKP | AVST_CLK period | 8 | ns |
tADSU 136 | AVST_DATA setup time before rising edge of AVST_CLK | 2.1 | ns |
tADH 136 | AVST_DATA hold time after rising edge of AVST_CLK | 0.1 | ns |
tAVSU | AVST_VALID setup time before rising edge of AVST_CLK | 2.1 | ns |
tAVDH | AVST_VALID hold time after rising edge of AVST_CLK | 0 | ns |
Figure 30. Avalon® Streaming Configuration Timing Diagram
136 Data sampled by the FPGA (sink) at the next rising clock edge.