Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 4/01/2024
Document Table of Contents

JTAG Configuration Timing

Table 88.  JTAG Timing Parameters and Values For specification status, see the Data Sheet Status table
Symbol Description Requirement Unit
Minimum Maximum
tJCP TCK clock period 30 ns
tJCH TCK clock high time 14 ns
tJCL TCK clock low time 14 ns
tJPSU (TDI) 129 TDI JTAG port setup time 2 ns
tJPSU (TMS) 129 TMS JTAG port setup time 3 ns
tJPH 129 JTAG port hold time 5 ns
tJPCO JTAG port clock to output 7130 ns
tJPZX JTAG port high impedance to valid output 14 ns
tJPXZ JTAG port valid output to high impedance 14 ns
Figure 27. JTAG Timing Diagram
129 For boundary-scan testing, the TMS and TDI JTAG ports minimum setup time and hold time are 7 ns.
130 Capacitance loading at 10 pF.