LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
External Configuration Clock Source Requirements
Description | External Clock Source | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
Clock input frequencyyvx1657772357609.html#ds_4_0c62482af87a__fn_oscclk-f1 | Powered by VCCIO_SDM | 25/100/125 | MHz | ||
Clock input peak-to-peak period jitter tolerance | — | — | 2 | % | |
Clock input duty cycle | 45 | 50 | 55 | % |
142 The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. You must match the external configuration clock frequency on the OSC_CLK_1 pin to the configuration clock source assignment in the Quartus® Prime software. Other frequencies in the range are not supported.