Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 4/01/2024
Document Table of Contents

External Configuration Clock Source Requirements

Table 87.  External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements For specification status, see the Data Sheet Status table
Description External Clock Source Min Typ Max Unit
Clock input frequency128 Powered by VCCIO_SDM 25/100/125 MHz
Clock input peak-to-peak period jitter tolerance 2 %
Clock input duty cycle 45 50 55 %
128 The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. You must match the external configuration clock frequency on the OSC_CLK_1 pin to the configuration clock source assignment in the Intel Quartus® Prime software. Other frequencies in the range are not supported.