Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

Download PDF
ID 769310
Date 9/05/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics
Electrical Characteristics x
Operating Conditions Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics I/O Standard Specifications
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

HPS I2C Timing Characteristics

Table 85.  HPS I2C Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Standard Mode Fast Mode Unit
Minimum Maximum Minimum Maximum
Tclk Serial clock (SCL) clock period 10 — 2.5 — μs
Tclk_jitter I2C clock output jitter — 2 — 2 %
THIGH aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f1 SCL high period 4aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f2 — 0.6aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f3 — μs
TLOW aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f4 SCL low period 4.7aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f5 — 1.3aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f6 — μs
TSU;DAT Setup time for serial data line (SDA) data to SCL 0.25 — 0.1 — μs
THD;DAT aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f7 Hold time for SCL to SDA data 0 3.15 0 0.6 μs
TVD;DAT and TVD;ACK aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f8 SCL to SDA output data delay — 3.45aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f9 — 0.9aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f10 μs
TSU;STA Setup time for a repeated start condition 4.7 — 0.6 — μs
THD;STA Hold time for a repeated start condition 4 — 0.6 — μs
TSU;STO Setup time for a stop condition 4 — 0.6 — μs
TBUF SDA high pulse duration between STOP and START 4.7 — 1.3 — μs
Tscl:r aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f11 SCL rise time — 1,000 20 300 ns
Tscl:f aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f11 SCL fall time — 300 6.54 300 ns
Tsda:r aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f11 SDA rise time — 1,000 20 300 ns
Tsda:f aza1657772286122.html#ds_11_75f27b7d6f7b__fn_hpsi2c-f11 SDA fall time — 300 6.54 300 ns
Figure 16. I2C Timing Diagram
Related Information
129 You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
130 The recommended minimum setting for ic_ss_scl_hcnt is 428. Refer to the related information for the SCL_High_time equation.
131 The recommended minimum setting for ic_fs_scl_hcnt is 75. Refer to the related information for the SCL_High_time equation.
132 You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
133 The recommended minimum setting for ic_ss_scl_lcnt is 464. Refer to the related information for the SCL_Low_time equation.
134 The recommended minimum setting for ic_fs_scl_lcnt is 163. Refer to the related information for the SCL_Low_time equation.
135 THD;DAT is affected by the rise and fall time.
136 TVD;DAT and TVD;ACK are affected by the rise and fall time, as well as the SDA hold time (set by adjusting the ic_sda_hold register).
137 Use maximum SDA_HOLD = 240 to be within the specification.
138 Use maximum SDA_HOLD = 60 to be within the specification.
139 Rise and fall time parameters vary depending on external factors such as the characteristics of the I/O driver, pull-up resistor value, and total capacitance on the transmission line.
Level Two Title