Visible to Intel only — GUID: rti1657772164795
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: rti1657772164795
Ixiasoft
DPA Lock Time Specifications
Standard | Training Pattern | Number of Data Transitions in One Repetition of the Training Pattern | Number of Repetitions per 256 Data Transitions80 | Maximum Data Transition |
---|---|---|---|---|
SPI-4 | 00000000001111111111 | 2 | 128 | 768 |
Parallel Rapid I/O | 00001111 | 2 | 128 | 768 |
10010000 | 4 | 64 | 768 | |
Miscellaneous | 10101010 | 8 | 32 | 768 |
01010101 | 8 | 32 | 768 |
80 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.