Visible to Intel only — GUID: oon1657772353539
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: oon1657772353539
Ixiasoft
General Configuration Timing Specifications
Symbol | Description | Requirement | Unit | |
---|---|---|---|---|
Min | Max | |||
tCF12ST1 | nCONFIG high to nSTATUS high | — | 20 | ms |
tCF02ST0 | nCONFIG low to nSTATUS low | — | 400 | ms |
tST0 | nSTATUS low pulse during configuration error | 0.5 | 10 | ms |
tCD2UM 127 | CONF_DONE high to user mode | — | 5 | ms |
tST12CF0 | Minimum time to drive nCONFIG from high to low after nSTATUS transitions from low to high | 0 | — | ms |
tST02CF1 | Minimum time to drive nCONFIG from low to high after nSTATUS transitions from high to low | 0 | — | ms |
Figure 26. General Configuration Timing Diagram
Note: CONF_DONE and INIT_DONE are de-asserted during device clean state after full device reconfiguration is triggered.
127 This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.