LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
I/O Standard | VCCIO_PIO (V) | Internal VREF (V) | VTT (V) | ||||||
---|---|---|---|---|---|---|---|---|---|
Minimum | Typical | Maximum | Minimum | Typical | Maximum | Minimum | Typical | Maximum | |
SSTL-12 | 1.14 | 1.2 | 1.26 | 0.49 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.51 × VCCIO_PIO | 0.45 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.55 × VCCIO_PIO |
HSTL-12 | 1.14 | 1.2 | 1.26 | 0.47 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.53 × VCCIO_PIO | 0.45 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.55 × VCCIO_PIO |
HSUL-1242 | 1.14 | 1.2 | 1.26 | 0.49 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.51 × VCCIO_PIO | 0.45 × VCCIO_PIO | 0.5 × VCCIO_PIO | 0.55 × VCCIO_PIO |
POD12 (GPIO)43 44 | 1.164 | 1.2 | 1.236 | 0.69 × VCCIO_PIO | 0.7 × VCCIO_PIO | 0.71 × VCCIO_PIO | — | VCCIO_PIO | — |
POD12 (PHYLITE)43 44 | 1.164 | 1.2 | 1.236 | 0.74 × VCCIO_PIO | 0.75 × VCCIO_PIO | 0.76 × VCCIO_PIO | — | VCCIO_PIO | — |
POD11 (GPIO)43 44 | 1.067 | 1.1 | 1.133 | 0.69 × VCCIO_PIO | 0.7 × VCCIO_PIO | 0.71 × VCCIO_PIO | — | VCCIO_PIO | — |
POD11 (PHYLITE)43 44 | 1.067 | 1.1 | 1.133 | 0.74 × VCCIO_PIO | 0.75 × VCCIO_PIO | 0.76 × VCCIO_PIO | — | VCCIO_PIO | — |
LVSTL1143 | 1.067 | 1.1 | 1.133 | 0.24 × VCCIO_PIO | 0.25 × VCCIO_PIO | 0.26 × VCCIO_PIO | — | GND | — |
LVSTL10543 | 1.0185 | 1.05 | 1.0815 | 0.24 × VCCIO_PIO | 0.25 × VCCIO_PIO | 0.26 × VCCIO_PIO | — | GND | — |
LVSTL700 | 1.0185 | 1.05 | 1.0815 | 0.174 × VCCIO_PIO | 0.184 × VCCIO_PIO | 0.194 × VCCIO_PIO | — | GND | — |
42 Usage of on-board receiver termination is optional.
43 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
- PHYLITE mode
- GPIO mode
44 For I/O lane with mixture of GPIO and PHYLITE interfaces, the VREF specification for that I/O lane follows the PHYLITE VREF specifications.