LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Recommended Operating Conditions
Symbol | Description | Condition | Minimumjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f1 | Typical | Maximumjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f1 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage power supply | SmartVID 14: –1V, –2V, –3V, –3E | (Typical) – 3% | 0.70 – 0.90jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f3 | (Typical) + 3% | V |
VCCP | Periphery circuitry power supply | SmartVID14: –1V, –2V, –3V, –3E | (Typical) – 3% | 0.70 – 0.90jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f3 | (Typical) + 3% | V |
VCCPT | Power supply for I/O PLL and I/O pre-driver | — | 1.71 | 1.8 | 1.89 | V |
VCCRCORE | CRAM power supply | — | 1.14 | 1.2 | 1.26 | V |
VCCH | Advanced interface bus (AIB) power supply | Devices with R-Tile and F-Tile | 0.776 | 0.8 | 0.824 | V |
Devices with F-Tile only | 0.776 | 0.8 | 0.824 | V | ||
VCCH_SDM | SDM block transceiver digital power sense | Devices with R-Tile and F-Tile | 0.87 | 0.9 | 0.93 | V |
Devices with F-Tile only | 0.776 | 0.8 | 0.824 | V | ||
VCCIO_UIB | Power supply for the Universal Interface Bus between the core and embedded HBM2E memory | — | 1.17 | 1.2 | 1.23 | V |
VCCIO_PIO_SDM jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f8 | SDM block I/O bank power sense of Bank 3A | 1.05 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f13 | 1.0185 | 1.05 | 1.0815 | V |
1.1 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f13 | 1.067 | 1.1 | 1.133 | V | ||
1.2 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f13 | 1.164 | 1.2 | 1.236 | V | ||
1.3 V | 1.261 | 1.3 | 1.339 | V | ||
VCCIO_SDM | SDM block configuration pins power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCL_SDM | SDM block core voltage power supply | — | 0.776 | 0.8 | 0.824 | V |
VCCFUSEWR_SDM | SDM block fuse writing power supply | — | 1.75 | 1.8 | 1.85 | V |
VCCPLLDIG_SDM | SDM block PLL digital power supply | — | 0.776 | 0.8 | 0.824 | V |
VCCPLL_SDM | SDM block PLL analog power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCM_PUMP_HBM | HBM2E power supply | — | 2.4 | 2.5 | 2.6 | V |
VCCBAT jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f4 | Battery back-up power supply (For design security volatile key register) | — | 1 | — | 1.8 | V |
IBAT | Battery back-up power supply (For design security volatile key register) | VCCBAT = 1.2 V | — | — | 200 | nA |
VCCADC | ADC voltage sensor power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCIO_PIO | I/O bank power supply | 1.05 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f13 | 1.0185 | 1.05 | 1.0815 | V |
1.1 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f13 | 1.067 | 1.1 | 1.133 | V | ||
1.2 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f13 | 1.164 | 1.2 | 1.236 | V | ||
1.3 V | 1.261 | 1.3 | 1.339 | V | ||
VCCIO_NOC | NOC configuration pins power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCPLL_NOC | NOC PLL analog power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCPLLDIG_NOC | NOC PLL digital power supply | — | 0.776 | 0.8 | 0.824 | V |
VCCLPLL_NOC | NOC PLL core voltage power supply | — | 0.776 | 0.8 | 0.824 | V |
VI jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f5 | DC input voltage | VCCIO_PIO = 1.05 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f9 jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f11 | –0.3 | — | VCCIO_PIO + 0.25 | V |
VCCIO_PIO = 1.1 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f9 jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f11 | –0.3 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_PIO = 1.2 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f9 jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f11 | –0.3 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_PIO = 1.3 Vjar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f9 jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f11 | –0.3 | — | VCCIO_PIO + 0.25 | V | ||
VCCIO_SDM = 1.8 V | –0.3 | — | VCCIO_SDM + 0.3 | V | ||
VCCIO_HPS = 1.8 V | –0.3 | — | VCCIO_HPS + 0.3 | V | ||
VO | Output voltage | VCCIO_PIO = 1.05 V, 1.1 V, 1.2 V, 1.3 V | 0 | — | VCCIO_PIO | V |
VCCIO_SDM = 1.8 V | 0 | — | VCCIO_SDM | V | ||
VCCIO_HPS = 1.8 V | 0 | — | VCCIO_HPS | V | ||
TJ | Operating junction temperature | Extended | 0jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f14 | — | 100jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f10 jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f12 | °C |
IFUSEWR_SDM | SDM fuse Current | Static | — | — | 50 | mA |
Dynamic average AC during sensing and programming | — | 0.6 | — | mA | ||
tRAMP jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f6 jar1657772087691.html#ds_5_ae30961a6ab3__fn_roc-f7 | Power supply ramp time | Standard POR | 200 μs | — | 100 ms | — |
13 This value describes the required voltage measured between the PCB power and ground ball during normal device operation. The voltage ripple includes both regulator DC ripple and the dynamic noise.
14 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.
15 The typical value is based on the SmartVID programmed value.
16 Must be powered up with the same voltage level as VCCIO_PIO_3AT at 1.2 V when using Avalon® streaming x16/x32 configuration schemes. Tie to VCCRCORE when not using Avalon® streaming x16/x32 configuration schemes, use the tighter tolerance requirement when the power rails have different tolerances.
17 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
- LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
- PHYLITE mode
- GPIO mode
18 Power up VCCBAT with a non-volatile battery power source when using the device security AES BBRAM key. When not using the AES BBRAM key, tie this pin to ground.
19 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
20 Applies to LVCMOS I/O standards only. For true differential input, refer to the VICM(min), VICM(max), and VID(max) specifications.
21 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the VI (DC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V.
22 Agilex™ 7 M-Series devices are generally offered in Extended temperature range only. If an industrial temperature range is required, note that you can configure these devices at less than 0°C, but the HBM2E interface will be held reset and not calibrated until Tj reaches 0°C. Contact your sales representative for the availability of Agilex™ 7 M-Series Industrial temperature range devices.
23 When using the device at TJ = 100°C, the device can operate under the recommended operating conditions over a minimum device lifetime of 11.4 years.
24 The recommended maximum operating temperature for HBM2E devices is 95°C.
25 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
26 To support AS fast mode, all power supplies to the device must be fully ramped-up within 10 ms to the recommended operating conditions.