LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
R-Tile Transceiver Reference Clock Specifications
Symbol/Description | Condition | All Transceiver Speed Grades | Unit | ||
---|---|---|---|---|---|
Minimum | Typical | Maximum | |||
Supported I/O standards | PCIe* | HCSL | — | ||
CXL | HCSL | — | |||
Refclk frequency for devices that support 32.0 GT/skqk1657772190954.html#ds_4_fe06fab704e1__fn_rrefclk-f1 | PCIe* | 99.99 | 100 | 100.01 | MHz |
CXL | 99.99 | 100 | 100.01 | MHz | |
Rising edge ratekqk1657772190954.html#ds_4_fe06fab704e1__fn_rrefclk-f2 | PCIe* | 0.6 | — | 4 | V/ns |
CXL | 0.6 | — | 4 | V/ns | |
Falling edge ratekqk1657772190954.html#ds_4_fe06fab704e1__fn_rrefclk-f2 | PCIe* | 0.6 | — | 4 | V/ns |
CXL | 0.6 | — | 4 | V/ns | |
Duty cycle | PCIe* | 40 | — | 60 | % |
CXL | 40 | — | 60 | % | |
Absolute VMAX | PCIe* | — | — | 1.15 | V |
CXL | — | — | 1.15 | V | |
Absolute VMIN | PCIe* | — | — | –0.3 | V |
CXL | — | — | –0.3 | V | |
Differential Input High Voltage (VIH) kqk1657772190954.html#ds_4_fe06fab704e1__fn_rrefclk-f4 | PCIe* | 150 | — | — | mV |
Differential Input High Voltage (VIH) kqk1657772190954.html#ds_4_fe06fab704e1__fn_rrefclk-f4 | CXL | 150 | — | — | mV |
Differential Input Low Voltage (VIL) kqk1657772190954.html#ds_4_fe06fab704e1__fn_rrefclk-f4 | PCIe* | — | — | -150 | mV |
Differential Input Low Voltage (VIL) kqk1657772190954.html#ds_4_fe06fab704e1__fn_rrefclk-f4 | CXL | — | — | -150 | mV |
Peak-to-peak differential input voltage | PCIe* | 300 | — | 1,450 | mV |
CXL | 300 | — | 1,450 | mV | |
Vcross | PCIe* | 250 | — | 550 | mV |
CXL | 250 | — | 550 | mV | |
Cycle-to-cycle jitter (TCCJITTER)kqk1657772190954.html#ds_4_fe06fab704e1__fn_rrefclk-f3 | PCIe* | — | — | 150 | ps |
CXL | — | — | 150 | ps | |
Spread-spectrum modulating clock frequency | PCIe* | 30 | — | 33 | kHz |
CXL | 30 | — | 33 | kHz | |
SSC deviation for devices that support 32.0 GT/s and SRIS when operating in SRIS mode at all speeds | PCIe* | –0.3 | — | 0 | % |
CXL | –0.3 | — | 0 | % | |
TSSC-MAX-PERIOD-SLEW | Max SSC df/dt for PCIe* | — | — | 1,250 | ppm/µs |
Max SSC df/dt for CXL | — | — | 1,250 | ppm/µs |
Related Information
92 This number is with spread-spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications in Section 8.6 Refclk Specifications of PCI Express* Base Specification Revision 5.0 Version 1.0.
93 Measured from –150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential zero crossing.
94 Measurement taken from differential waveform.
95 For common reference clock architecture, you must meet the jitter limit specified in Section 8.6 Refclk Specifications of PCI Express* Base Specification Revision 5.0 Version 1.0.