Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 4/01/2024
Document Table of Contents

HPS USB UPLI Timing Characteristics

Table 72.  HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tusb_clk USB_CLK clock period 16.667 ns
Td Clock to USB_STP/USB_DATA[7:0] output delay 2 7 ns
Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 4 ns
Th Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] 4 ns
Figure 10. USB ULPI Timing Diagram
Note: The USB interface supports single data rate (SDR) timing only.