Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 9/05/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics
Electrical Characteristics x
Operating Conditions Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics I/O Standard Specifications
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

HPS USB UPLI Timing Characteristics

Table 78.  HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Minimum Typical Maximum Unit
Tusb_clk USB_CLK clock period — 16.667 — ns
Td Clock to USB_STP/USB_DATA[7:0] output delay 2 — 7 ns
Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 4 — — ns
Th Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] 1 — — ns
Figure 10. USB ULPI Timing Diagram
Note: The USB interface supports single data rate (SDR) timing only.
Note: If you need to adjust the timings of certain signals, you can use the HPS registers Pin_Mux.io0_delay through Pin_Mux.io47_delay to allow software to set the delay chains in each of the dedicated I/Os. For example, to add output and input delay to the USB_DATA3 signal (HPS_IOA_8), program Pin_Mux.io7_delay.output_val_en = 1, and Pin_Mux.io7_delay.output_val = 15 to add approximately 1.6 ns output delay from the HPS, and program Pin_Mux.io7_delay.input_val_en = 3, and Pin_Mux.io7_delay.input_val = 30 to add approximately 2.9 ns input delay into the HPS. See HPS Programmable I/O Timing Characteristics for more information.
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