Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 9/05/2025
Public
Document Table of Contents

Table 32.  GPIO-B Differential LVSTL I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (%)49
Minimum Typical Maximum Maximum Minimum Maximum Minimum Maximum
LVSTL1150 1.067 1.1 1.133 –0.11 0.11 –0.14 0.14 25
LVSTL10550 1.0185 1.05 1.0815 –0.11 0.11 –0.14 0.14 25
LVSTL700 1.0185 1.05 1.0815 –0.11 0.11 –0.14 0.14 25
Note: For eye height position estimation in EMIF interfaces, refer to the External Memory Interfaces Agilex™™ 7 M-Series FPGA IP User Guide. The eye mask estimation methodology defined in the External Memory Interfaces Agilex™™ 7 M-Series FPGA IP User Guide takes precedence over specifications in GPIO-B Differential LVSTL I/O Standards Specifications table.
49 Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
50 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
  • PHYLITE mode
  • GPIO mode