Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 9/05/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics
Electrical Characteristics x
Operating Conditions Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics I/O Standard Specifications
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

HPS NAND Timing Characteristics

Table 86.  HPS NAND ONFI 1.0 Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Minimum Maximum Unit
TWP qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Write enable pulse width 10 — ns
TWH qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Write enable hold time 7 — ns
TRP qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Read enable pulse width 10 — ns
TREH qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Read enable hold time 7 — ns
TCLS qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Command latch enable to write enable setup time 10 — ns
TCLH qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Command latch enable to write enable hold time 5 — ns
TCS qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Chip enable to write enable setup time 15 — ns
TCH qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Chip enable to write enable hold time 5 — ns
TALS qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Address latch enable to write enable setup time 10 — ns
TALH qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Address latch enable to write enable hold time 5 — ns
TDS qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Data to write enable setup time 7 — ns
TDH qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Data to write enable hold time 5 — ns
TWB qte1657772324122.html#ds_12_45f31280bc07__fn_hpsnand-f1 Write enable high to R/B low — 200 ns
TCEA Chip enable to data access time — 100 ns
TREA Read enable to data access time — 40 ns
TRHZ Read enable to data high impedance — 200 ns
TRR Ready to read enable low 20 — ns
Figure 17. NAND Command Latch Timing Diagram
Figure 18. NAND Address Latch Timing Diagram
Figure 19. NAND Data Output Cycle Timing Diagram
Figure 20. NAND Data Input Cycle Timing Diagram
Figure 21. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 22. NAND Read Status Timing Diagram
Figure 23. NAND Read Status Enhanced Timing Diagram
Related Information
140 This timing is software programmable. Refer to the related information for more information about software-programmable timing in the NAND flash controller.
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