Visible to Intel only — GUID: qte1657772324122
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: qte1657772324122
Ixiasoft
HPS NAND Timing Characteristics
Symbol | Description | Min | Max | Unit |
---|---|---|---|---|
TWP 126 | Write enable pulse width | 10 | — | ns |
TWH 126 | Write enable hold time | 7 | — | ns |
TRP 126 | Read enable pulse width | 10 | — | ns |
TREH 126 | Read enable hold time | 7 | — | ns |
TCLS 126 | Command latch enable to write enable setup time | 10 | — | ns |
TCLH 126 | Command latch enable to write enable hold time | 5 | — | ns |
TCS 126 | Chip enable to write enable setup time | 15 | — | ns |
TCH 126 | Chip enable to write enable hold time | 5 | — | ns |
TALS 126 | Address latch enable to write enable setup time | 10 | — | ns |
TALH 126 | Address latch enable to write enable hold time | 5 | — | ns |
TDS 126 | Data to write enable setup time | 7 | — | ns |
TDH 126 | Data to write enable hold time | 5 | — | ns |
TWB 126 | Write enable high to R/B low | — | 200 | ns |
TCEA | Chip enable to data access time | — | 100 | ns |
TREA | Read enable to data access time | — | 40 | ns |
TRHZ | Read enable to data high impedance | — | 200 | ns |
TRR | Ready to read enable low | 20 | — | ns |
Figure 17. NAND Command Latch Timing Diagram
Figure 18. NAND Address Latch Timing Diagram
Figure 19. NAND Data Output Cycle Timing Diagram
Figure 20. NAND Data Input Cycle Timing Diagram
Figure 21. NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
Figure 22. NAND Read Status Timing Diagram
Figure 23. NAND Read Status Enhanced Timing Diagram
126 This timing is software programmable. Refer to the related information for more information about software-programmable timing in the NAND flash controller.