Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 9/05/2025
Public
Document Table of Contents

HPS PLL Specifications

Table 72.  HPS PLL Input Requirements

The main HPS PLL receives its clock signals from the HPS_OSC_CLK pin. Refer to the related information for information about assigning this pin.

For specification status, see the Data Sheet Status table

Description Minimum Typical Maximum Unit
Clock input range 25 125 MHz
Clock input accuracy 50 ppm
Clock input duty cycle 45 50 55 %
Table 73.  HPS PLL Performance For specification status, see the Data Sheet Status table
Description Minimum Maximum Unit
Main PLL VCO output 3,000 MHz
Peripheral PLL VCO output 3,000 MHz
h2f_user0_clkdpl1657772217429.html#ds_5_85a9f25298f7__fn_hpspll-f1 500 MHz
h2f_user1_clkdpl1657772217429.html#ds_5_85a9f25298f7__fn_hpspll-f1 500 MHz
119 The HPS PLL provides this clock to the FPGA fabric.