LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
HPS Power Supply Operating Conditions
Symbol | Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCL_HPS | HPS core voltage and periphery circuitry power supply | Performance boost, fixed voltage: –1V | (Typical) – 3% | 0.95 | (Typical) + 3% | V |
SmartVID: –1V, –2V, –3V, –3E 33 | (Typical) – 3% | 0.70 – 0.90 | (Typical) + 3% | V | ||
VCCPLLDIG_HPS | HPS PLL digital power supply (can be connected to VCCL_HPS) | Performance boost, fixed voltage: –1V | (Typical) – 3% | 0.95 | (Typical) + 3% | V |
SmartVID: –1V, –2V, –3V, –3E 33 | (Typical) – 3% | 0.70 – 0.90 | (Typical) + 3% | V | ||
VCCPLL_HPS | HPS PLL analog power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO_HPS | HPS I/O buffers power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
33 The use of Power Management Bus (PMBus*) voltage regulator dedicated to SmartVID devices is mandatory. The PMBus* voltage regulator and SmartVID devices are connected via PMBus*.