Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS and SDM I/O DC Characteristics
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS and SDM I/O DC Characteristics x
HPS and SDM I/O Pin Leakage Current HPS and SDM I/O Pin Capacitance HPS and SDM I/O Internal Weak Pull-Up Resistor HPS and SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS and SDM I/O Standard Specifications
GPIO-B I/O Standard Specifications x
GPIO-B Single-Ended I/O Standards Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications GPIO-B Single-Ended LVSTL I/O Standards Specifications GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications GPIO-B Differential POD I/O Standards Specifications GPIO-B Differential LVSTL I/O Standards Specifications GPIO-B Differential I/O Standards Specifications
HPS and SDM I/O Standard Specifications x
HPS and SDM Single-Ended I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, the toggling input data or clock signals may overshoot to the voltage listed in the following tables and undershoot to the following limits for input currents less than 100 mA and periods shorter than 20 ns.
  • Undershoot limit of –1.1 V when using VCCIO_HPS or VCCIO_SDM of 1.8 V.
  • Undershoot limit of –0.3 V when using VCCIO_PIO of 1.3 V, 1.2 V , 1.1 V, and 1.05 V.

No overshooting beyond 1.602 V and undershooting below 0.273 V is allowed when using True Differential Signaling I/O standard at VCCIO_PIO = 1.3 V.

No overshooting beyond 1.177 V and undershooting below 0.573 V is allowed when using True Differential Signaling I/O standard at VCCIO_PIO = 1.2 V, 1.1 V, and 1.05 V.

The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) × 100) over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

Table 4.  Maximum Allowed Overshoot During Transitions (for 1.05 V I/O in GPIO-B Bank)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.309 30 %
VCCIO_PIO + 0.35 4 %
> VCCIO_PIO + 0.40 No Overshoot Allowed %
Table 5.  Maximum Allowed Overshoot During Transitions (for 1.1 V I/O in GPIO-B Bank)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.3010 30 %
VCCIO_PIO + 0.35 4 %
> VCCIO_PIO + 0.40 No Overshoot Allowed %
Table 6.  Maximum Allowed Overshoot During Transitions (for 1.2 V I/O in GPIO-B Bank)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.3011 30 %
VCCIO_PIO + 0.35 4 %
> VCCIO_PIO + 0.40 No Overshoot Allowed %
Table 7.  Maximum Allowed Overshoot During Transitions (for 1.3 V I/O in GPIO-B Bank)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.25 100 %
VCCIO_PIO + 0.3012 65 %
VCCIO_PIO + 0.35 7 %
> VCCIO_PIO + 0.40 No Overshoot Allowed %
Table 8.  Maximum Allowed Overshoot During Transitions (for 1.8 V I/O in HPS and SDM I/O Banks)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_SDM + 0.30, VCCIO_HPS + 0.30 100 %
VCCIO_SDM + 0.35, VCCIO_HPS + 0.35 60 %
VCCIO_SDM + 0.40, VCCIO_HPS + 0.40 30 %
VCCIO_SDM + 0.45, VCCIO_HPS + 0.45 20 %
VCCIO_SDM + 0.50, VCCIO_HPS + 0.50 10 %
VCCIO_SDM + 0.55, VCCIO_HPS + 0.55 6 %
> VCCIO_SDM + 0.55, > VCCIO_HPS + 0.55 No Overshoot Allowed %

For example, when using 1.2 V I/O standard with 1.26 V VCCIO_PIO, a signal that overshoots to 1.61 V can only be at 1.61 V for ~4% over the lifetime of the device. For an overshoot of 1.51 V, the percentage of high time for the overshoot can be as high as 100% over the lifetime of the device.

Figure 1. Overshoot Duration Example (for 1.2 V GPIO-B Bank at VCCIO_PIO = 1.26 V)
9 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.
10 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.
11 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.
12 For LVCMOS pin utilization of equal to or less than 25 pins within a bank, the Vi (AC) for the LVCMOS input can go up to VCCIO_PIO + 0.3 V at an overshoot duration of 100%.
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