LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
F-Tile Receiver Specifications
Parameter | Symbol | Description | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
Receiver input eye specifications | VRX-DIFF-PKPK | Receiver input differential peak-to-peak voltagerqg1657772206646.html#ds_6_8799ea2f66b5__fn_fhtrx-f2 | Closed eye | — | 1,200 | mVdiff-pkpk |
VRX-CM-DC | Receiver input DC common-mode voltagerqg1657772206646.html#ds_6_8799ea2f66b5__fn_fhtrx-f1 [fhtrx-f2] | 100 | — | 900 | mV | |
VRX-MAX | Receiver input maximum voltagerqg1657772206646.html#ds_6_8799ea2f66b5__fn_fhtrx-f2 | — | — | 1,200 | mV | |
VRX-MIN | Receiver input minimum voltage | –200 | — | — | mV | |
TRX-DDJ | Receive input signal data dependent jitter (inter-symbol interference) | — | — | 1 | UIpkpk | |
TRX-RJ | Receive input random jitter | — | — | 0.15 | UIpkpk | |
TRX-PJ | Receive input periodic jitter (at high frequency) | — | — | 0.05 | UIpkpk | |
TRX-TJ | Receive input total jitter (DDJ + RJ + PJ) | — | — | 1 | UIpkpk | |
Equalizer specifications | FPPM-OFFSET | Tolerable data frequency offset | –200 | — | 200 | ppm |
Receiver return loss | ZRL-DIFF-DC | Receiver differential DC return loss | — | — | 10 | dB |
ZRL-DIFF-NYQ | Receiver differential return loss at Nyquist frequency (FBAUD/2) | — | — | 6 | dB | |
ZRL-CM | Receiver common-mode return loss below 10 GHz | — | — | 6 | dB | |
Receiver DC impedance | RDIFF-DC | DC differential receive impedance | 80 | 100 | 120 | Ω |
RCM-DC | DC common-mode receive impedance | 20 | 25 | 30 | Ω |
Parameter | Symbol | Description | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
Receiver input eye specifications | VRX-DIFF-PKPK | Receiver input differential peak-to-peak voltagerqg1657772206646.html#ds_6_8799ea2f66b5__fn_fgtrx-f6 | Closed eye | — | 1,200 | mV |
VRX-MAX | Receiver input maximum voltagerqg1657772206646.html#ds_6_8799ea2f66b5__fn_fgtrx-f4 | — | — | 1 | V | |
VRX-MIN | Receiver input minimum voltagerqg1657772206646.html#ds_6_8799ea2f66b5__fn_fgtrx-f4 | –0.3 | — | — | V | |
VRX-CM-DC | Receiver input DC common-mode voltagerqg1657772206646.html#ds_6_8799ea2f66b5__fn_fgtrx-f1 | 0 | — | 700 | mV | |
TRX-RJ | Receive input random jitter | — | — | 0.15 | UIpkpk | |
TRX-PJ | Receive input periodic jitter (at high frequency) | — | — | 0.05 | UIpkpk | |
Insertion loss specifications | IINS-LOSS-56Gb/s | Insertion loss at 56 Gbps PAM42/BER <10–4 | — | — | 30 | dB |
IINS-LOSS-53Gb/s | Insertion loss at 53 Gbps PAM42/BER <10–4 | 5rqg1657772206646.html#ds_6_8799ea2f66b5__fn_fgtrx-f3 | — | — | dB | |
IINS-LOSS-30Gb/s | Insertion loss at 32 Gbps NRZrqg1657772206646.html#ds_6_8799ea2f66b5__fn_fgtrx-f2 /BER <10–12 | — | — | 30 | dB | |
IINS-LOSS-25Gb/s | Insertion loss at 25.78125 Gbps NRZrqg1657772206646.html#ds_6_8799ea2f66b5__fn_fgtrx-f2/ BER <10–12 | — | — | 30 | dB | |
Receiver return loss | ZRL-DIFF-DC | Receiver differential DC return loss | — | — | 12 | dB |
ZRL-DIFF-NYQ | Receiver differential return loss at Nyquist frequency (FBAUD/2) | — | — | 6 | dB | |
ZRL-CM | Receiver common-mode return loss below 10 GHz | — | — | 6 | dB | |
Receiver DC impedance | RDIFF-DC | DC differential receive impedance | 65 | 85 | 102 | Ω |
80 | 100 | 120 | Ω | |||
RCM-DC | DC common-mode receive impedance | 20 | 25 | 30 | Ω | |
Receiver signal detectionrqg1657772206646.html#ds_6_8799ea2f66b5__fn_fgtrx-f5 | VIDLE-THRESH | Receiver signal detect input voltage threshold | 75 | 120 | 175 | mVdiff-pkpk |
109 To support Hot Swap with FHT PMA’s, ensure the following:
For AC Coupled connections:
- RX inputs have external AC coupling caps of at least 100nF.
- The single-ended voltages applied to the RX_p and RX_n pins should not exceed ±300mV (for a total of 600mV p-p).
- The total differential voltage (combination of RX_p/RX_n) should not exceed 1,200mV.
- The FHT RX Analog Parameter selection for External AC cap must be EXTERNAL_AC_CAP_ENABLE.
- The maximum amount of time that the unpowered FHT RX PMA can be DC coupled to a link partner who is transmitting is 40 minutes. If you cannot meet this requirement, contact Altera Customer Support.
- The single-ended voltages applied to the RX_p and RX_n pins should not exceed ±300mV (for a total of 600mV p-p).
- The total differential voltage (combination of RX_p/RX_n) should not exceed 1,200mV.
- The FHT RX Analog Parameter selection for External AC cap must be EXTERNAL_AC_CAP_DISABLE.
110 Referenced to RX GND. This specification is also supported before mode configuration.
111 This is supported when the receiver is powered and configured, powered and unconfigured, or unpowered.
112 VRX_MAX and VRX_MIN are before and after configuration.
113 The specified common-mode range is supported when the receiver is powered and configured, powered and unconfigured, or unpowered. This specification is also supported before mode configuration. If squelch detect is used, receiver DC input common-mode voltage should be within 200 mV to 300 mV. Otherwise, use AC coupling capacitors on board.
114 The minimum insertion loss specification assumes a PAM4 transmitter with 800 mVppd. For transmitters with output amplitude adjustment capabilities and can reduce output amplitude to below 800 mVppd, this minimum insertion loss can be further relaxed.
115 COM compliant package and channel.
116 Receiver signal detection values in this table are applicable to PCIe* and similar standards, such as SATA, where a clock pattern like PCIe* EIEOS 500 MHz clock pattern is used.