Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 7/13/2023
Document Table of Contents

I/O Timing

I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually using the Timing Analyzer.

The Intel Quartus® Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route.

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