Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 9/05/2025
Public
Document Table of Contents

Table 30.  GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (V) VOX(AC) (V)
Minimum Typical Maximum Maximum Minimum Maximum Minimum Minimum Typical Maximum Minimum Typical Maximum
SSTL-12wjc1657772119606.html#ds_13_c245716699ee__fn_diffshh-f1 1.14 1.2 1.26 –0.15 0.15 –0.2 0.2 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12
HSTL-12wjc1657772119606.html#ds_13_c245716699ee__fn_diffshh-f1 1.14 1.2 1.26 –0.16 0.16 –0.3 0.3 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12
HSUL-12wjc1657772119606.html#ds_13_c245716699ee__fn_diffshh-f1 1.14 1.2 1.26 –0.2 0.2 –0.27 0.27 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12
46 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
  • PHYLITE mode
  • GPIO mode