Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 9/05/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics
Electrical Characteristics x
Operating Conditions Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics I/O Standard Specifications
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

R-Tile Receiver Specifications

Table 57.  R-Tile Receiver Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition All Transceiver Speed Grades Unit
Minimum Typical Maximum
Supported I/O standards PCIe* High-Speed Differential I/O —
CXL High-Speed Differential I/O —
Peak-to-peak differential input voltage VID (diff p-p) PCIe* 2.5 GT/sksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f1 175 — 1,200 mVPP
PCIe* 5.0 GT/sksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f1 100 — 1,200 mVPP
PCIe* 8.0 GT/sksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f1 25 — 1,200 mVPP
PCIe* 16.0 GT/sksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f1 15 — 800 mVPP
PCIe* 32.0 GT/sksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f1 15 — 800 mVPP
CXL 8.0 GT/sksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f1 25 — 1,200 mVPP
CXL 16.0 GT/sksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f1 15 — 800 mVPP
CXL 32.0 GT/sksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f1 15 — 800 mVPP
Differential on-chip termination resistors PCIe* ksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f3 80 85 120 Ω
CXLksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f3 80 85 120 Ω
RCOMP PCIe* ksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f2 148.5 150 151.5 Ω
CXLksk1657772195784.html#ds_6_d3f4421f6317__fn_rrx-f2 148.5 150 151.5 Ω
97 For PCIe* at 2.5 GT/s and 5 GT/s, VID is measured at TP2, which is the accessible test point at the device under test. For PCIe* and CXL 8.0 GT/s, 16.0 GT/s and 32.0 GT/s, VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
98 85ohms (Typical) aligned to Base spec.
99 Connecting RCOMP at 150 Ω calibrates PCIe* and CXL channel on-chip termination to 85 Ω (aligned to Base spec).
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