Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

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ID 769310
Date 9/05/2025
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics
Electrical Characteristics x
Operating Conditions Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics I/O Standard Specifications
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

LVDS SERDES Specifications

Table 45.  LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 4 and 8.

DDR registers support SERDES factor J = 1 to 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table
Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade Unit
Minimum Typical Maximum Minimum Typical Maximum Minimum Typical Maximum
Clock frequency fHSCLK_in (input clock frequency) True Differential Signaling I/O Standards Clock boost factor W = 1 to 40dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f1 10 — 800 10 — 800 10 — 625 MHz
fHSCLK_in (input clock frequency) SLVS400 I/O Standards Clock boost factor W = 1 to 40dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f1 10 — 445.5 10 — 445.5 10 — 445.5 MHz
fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor W = 1 to 40dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f1 10 — 625 10 — 625 10 — 525 MHz
fHSCLK_OUT (output clock frequency) — — — 800 — — 800 — — 625 MHz
Transmitter True Differential Signaling I/O Standards - fHSDR (data rate)dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f2 SERDES factor J = 4 and 8dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f3 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f4 600 — 1,600 600 — 1,600 600 — 1,250 Mbps
SERDES factor J = 2, uses DDR registers dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 500dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 500dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 500dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 Mbps
SERDES factor J = 1, uses DDR registers dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 250dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 250dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 250dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 Mbps
tx Jitter - True Differential Signaling I/O Standards Total jitter for data rate, 600 Mbps – 1.6 Gbps ≤1,600 Mbps: 150

≤1,434 Mbps: 160

≤1,250 Mbps: 170

≤1,000 Mbps: 190

≤800 Mbps: 220

600 Mbps: 260

 ≤1,600 Mbps: 150

≤1,434 Mbps: 160

≤1,250 Mbps: 170

≤1,000 Mbps: 190

≤800 Mbps: 220

600 Mbps: 260

 ≤1,250 Mbps: 170

≤1,000 Mbps: 190

≤800 Mbps: 220

600 Mbps: 260

 ps
tDUTY dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f7 TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 45 50 55 %
tRISE & tFALL dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f8 True Differential I/O Standards — — 160 — — 180 — — 200 ps
TCCS dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f2 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f7 True Differential I/O Standards — — 202 — — 202 — — 202 ps
Receiverdwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f10 True Differential Signaling I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 and 8dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f3 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f4 600 — 1600dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f11 600 — 1600dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f11 600 — 1250dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f11 Mbps
SLVS400 I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 and 8dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f3 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f4 600 — 891 600 — 891 600 — 891 Mbps
fHSDR (data rate) (without DPA)dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f2 SERDES factor J = 4 and 8dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f3 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f4 150 — dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f9 150 — dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f9 150 — dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f9 Mbps
SERDES factor J = 2, uses DDR registers dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 500dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 500dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 500dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 Mbps
SERDES factor J = 1, uses DDR registers dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 250dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 250dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f5 — 250dwg1657772161891.html#ds_2_0aec7767a4cf__fn_lvds-f6 Mbps
DPA (FIFO mode) DPA run length — — — ≤10,000 — — ≤10,000 — — ≤10,000 UI
DPA (soft CDR mode) DPA run length SGMII/GbE protocol — — 5 — — 5 — — 5 UI
All other protocols — — 50 data transition per 208 UI — — 50 data transition per 208 UI — — 50 data transition per 208 UI —
Soft CDR mode Soft-CDR ppm tolerance — –300 — 300 –300 — 300 –300 — 300 ppm
Non DPA mode Sampling window — — — 330 — — 330 — — 330 ps
78 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
79 Requires package skew compensation with PCB trace length.
80 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
81 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
82 The minimum specification depends on the following factors. The differential I/O buffer within the IOE does not have a minimum data rate.
  • The clock source, such as the PLL and clock pin
  • The clock and data routing resource
83 You must perform design timing analysis in Quartus® Prime to achieve timing closure and run IBIS/HSPICE simulations to ensure that the I/O buffer's electrical performance meets the interface requirements.
84 Not applicable for DIVCLK = 1.
85 This applies to default pre-emphasis and VOD settings only.
86 You must enable the receiver equalization feature of the input buffer when operating in DPA mode.
87 1.05 V, 1.1 V, and 1.2 V True Differential Signaling I/O standards on receiver supports data rate up to 1000 Mbps.
88 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Level Two Title