LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
LVDS SERDES Specifications
Parameter | Symbol | Condition | –1 Speed Grade | –2 Speed Grade | –3 Speed Grade | Unit | ||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Minimum | Typical | Maximum | Minimum | Typical | Maximum | Minimum | Typical | Maximum | ||||
Clock frequency | fHSCLK_in (input clock frequency) True Differential Signaling I/O Standards | Clock boost factor W = 1 to 4078 | 10 | — | 800 | 10 | — | 800 | 10 | — | 625 | MHz |
fHSCLK_in (input clock frequency) SLVS400 I/O Standards | Clock boost factor W = 1 to 4078 | 10 | — | 445.5 | 10 | — | 445.5 | 10 | — | 445.5 | MHz | |
fHSCLK_in (input clock frequency) Single-Ended I/O Standards | Clock boost factor W = 1 to 4078 | 10 | — | 625 | 10 | — | 625 | 10 | — | 525 | MHz | |
fHSCLK_OUT (output clock frequency) | — | — | — | 800 | — | — | 800 | — | — | 625 | MHz | |
Transmitter | True Differential Signaling I/O Standards - fHSDR (data rate)79 | SERDES factor J = 4 and 880 81 | 600 | — | 1,600 | 600 | — | 1,600 | 600 | — | 1,250 | Mbps |
SERDES factor J = 2, uses DDR registers | 82 | — | 50083 | 82 | — | 50083 | 82 | — | 50083 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 82 | — | 25083 | 82 | — | 25083 | 82 | — | 25083 | Mbps | ||
tx Jitter - True Differential Signaling I/O Standards | Total jitter for data rate, 600 Mbps – 1.6 Gbps | ≤1,600 Mbps: 150 ≤1,434 Mbps: 160 ≤1,250 Mbps: 170 ≤1,000 Mbps: 190 ≤800 Mbps: 220 600 Mbps: 260 |
≤1,600 Mbps: 150 ≤1,434 Mbps: 160 ≤1,250 Mbps: 170 ≤1,000 Mbps: 190 ≤800 Mbps: 220 600 Mbps: 260 |
≤1,250 Mbps: 170 ≤1,000 Mbps: 190 ≤800 Mbps: 220 600 Mbps: 260 |
ps | |||||||
tDUTY 84 | TX output clock duty cycle for Differential I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE & tFALL 82 85 | True Differential I/O Standards | — | — | 160 | — | — | 180 | — | — | 200 | ps | |
TCCS 79 84 | True Differential I/O Standards | — | — | 202 | — | — | 202 | — | — | 202 | ps | |
Receiver86 | True Differential Signaling I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 and 880 81 | 600 | — | 160087 | 600 | — | 160087 | 600 | — | 125087 | Mbps |
SLVS400 I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 and 880 81 | 600 | — | 891 | 600 | — | 891 | 600 | — | 891 | Mbps | |
fHSDR (data rate) (without DPA)79 | SERDES factor J = 4 and 880 81 | 150 | — | 88 | 150 | — | 88 | 150 | — | 88 | Mbps | |
SERDES factor J = 2, uses DDR registers | 82 | — | 50083 | 82 | — | 50083 | 82 | — | 50083 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 82 | — | 25083 | 82 | — | 25083 | 82 | — | 25083 | Mbps | ||
DPA (FIFO mode) | DPA run length | — | — | — | ≤10,000 | — | — | ≤10,000 | — | — | ≤10,000 | UI |
DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | — | — | 5 | — | — | 5 | — | — | 5 | UI |
All other protocols | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | ||
Soft CDR mode | Soft-CDR ppm tolerance | — | –300 | — | 300 | –300 | — | 300 | –300 | — | 300 | ppm |
Non DPA mode | Sampling window | — | — | — | 330 | — | — | 330 | — | — | 330 | ps |
78 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
79 Requires package skew compensation with PCB trace length.
80 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
81 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
82 The minimum specification depends on the following factors. The differential I/O buffer within the IOE does not have a minimum data rate.
- The clock source, such as the PLL and clock pin
- The clock and data routing resource
83 You must perform design timing analysis in Quartus® Prime to achieve timing closure and run IBIS/HSPICE simulations to ensure that the I/O buffer's electrical performance meets the interface requirements.
84 Not applicable for DIVCLK = 1.
85 This applies to default pre-emphasis and VOD settings only.
86 You must enable the receiver equalization feature of the input buffer when operating in DPA mode.
87 1.05 V, 1.1 V, and 1.2 V True Differential Signaling I/O standards on receiver supports data rate up to 1000 Mbps.
88 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.