Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

Download PDF
ID 769310
Date 9/05/2025
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series x
Electrical Characteristics
Electrical Characteristics x
Operating Conditions Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: M-Series
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics
Recommended Operating Conditions x
Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption GPIO-B DC Characteristics HPS I/O DC Characteristics SDM I/O DC Characteristics I/O Standard Specifications
GPIO-B DC Characteristics x
GPIO-B I/O Pin Leakage Current GPIO-B OCT Calibration Accuracy Specifications GPIO-B OCT Without Calibration Resistance Tolerance Specifications GPIO-B Pin Capacitance GPIO-B Internal Weak Pull-Up Resistor
HPS I/O DC Characteristics x
HPS I/O Pin Leakage Current HPS I/O Pin Capacitance HPS I/O Internal Weak Pull-Up Resistor HPS I/O Hysteresis Specifications for Schmitt Trigger Input
SDM I/O DC Characteristics x
SDM I/O Pin Leakage Current SDM I/O Pin Capacitance SDM I/O Internal Weak Pull-Up Resistor SDM I/O Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
GPIO-B I/O Standard Specifications HPS I/O Standard Specifications SDM I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported Memory Output Clock Jitter Specifications Performance Specifications of the HBM2E Interface Performance Specifications of Network on Chip (NoC) NOC Reference Clock Requirements
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

Table 33.  GPIO-B Differential I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VID (mV) VICM(DC) (V) VOD (mV)fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f1 fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f2 VOCM (V)fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f1
Minimum Typical Maximum Minimum Maximum Minimum Condition Maximum Minimum Typical Maximum Minimum Typical Maximum
True Differential Signaling-1.3 V (LVDS compatible Transmitter and Receiver)fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f3 fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f5 fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f6 1.261 1.3 1.339 100 500 0.5 — 1.40fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f4 247 — 454 0.9 1 1.1
True Differential Signaling-1.2V (Receiver only)fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f3 1.14 1.2 1.26 100 454 0.8 — 0.95 — — — — — —
True Differential Signaling-1.1V (Receiver only)fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f3 1.045 1.1 1.155 100 454 0.8 — 0.95 — — — — — —
True Differential Signaling-1.05V (Receiver only)fmr1657772125669.html#ds_16_8cd86ec89590__fn_diffio-f3 0.9975 1.05 1.1025 100 454 0.8 — 0.95 — — — — — —
SLVS400 1.164 1.2 1.236 70 — 0.07 0.2 0.33 — — — — — —
1.067 1.1 1.133
51 RL range: 90 ≤ RL ≤ 110 Ω.
52 The specification is only applicable to default VOD and pre-emphasis setting.
53 The True Differential Signaling input buffer is supported on 1.05 V, 1.1 V, 1.2 V, and 1.3 V VCCIO_PIO bank. The maximum input voltage driven into the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.
54 True Differential Signaling - 1.3 V standard is compatible with LVDS and capable to interface with LVDS subsets such as:
  • RSDS
  • Mini-LVDS
  • Any I/O standards using equivalent electrical specifications
55 For further information on True Differential Signaling - 1.3 V feature support and guidelines on interfacing True Differential Signaling -1.3V standard with LVDS and it's subset compliant standards, refer to the related information.
56 The VICM(DC) voltage must not exceed 1.2 V when on-chip differential termination (RD OCT) is disabled with the use of external on-board termination.
Level Two Title