Visible to Intel only — GUID: fmr1657772125669
Ixiasoft
GPIO-B Single-Ended I/O Standards Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, POD and LVSTL I/O Reference Voltage Specifications
GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
GPIO-B Single-Ended LVSTL I/O Standards Specifications
GPIO-B Differential SSTL, HSTL, and HSUL I/O Standards Specifications
GPIO-B Differential POD I/O Standards Specifications
GPIO-B Differential LVSTL I/O Standards Specifications
GPIO-B Differential I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: fmr1657772125669
Ixiasoft
GPIO-B Differential I/O Standards Specifications
I/O Standard | VCCIO_PIO (V) | VID (mV) | VICM(DC) (V) | VOD (mV)47 48 | VOCM (V)47 | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
True Differential Signaling-1.3V (Transmitter & Receiver)49 | 1.261 | 1.3 | 1.339 | 100 | 454 | 0.5 | — | 1.37550 | 247 | — | 454 | 0.9 | 1 | 1.1 |
True Differential Signaling-1.2V (Receiver only)49 | 1.14 | 1.2 | 1.26 | 100 | 454 | 0.8 | — | 0.95 | — | — | — | — | — | — |
True Differential Signaling-1.1V (Receiver only)49 | 1.045 | 1.1 | 1.155 | 100 | 454 | 0.8 | — | 0.95 | — | — | — | — | — | — |
True Differential Signaling-1.05V (Receiver only)49 | 0.9975 | 1.05 | 1.1025 | 100 | 454 | 0.8 | — | 0.95 | — | — | — | — | — | — |
SLVS400 | 1.164 | 1.2 | 1.236 | 70 | — | 0.07 | 0.2 | 0.33 | 140 | 200 | 270 | 0.15 | 0.2 | 0.25 |
1.067 | 1.1 | 1.133 |
47 RL range: 90 ≤ RL ≤ 110 Ω.
48 The specification is only applicable to default VOD and pre-emphasis setting.
49 The True Differential Signaling input buffer is supported on 1.05 V, 1.1 V, 1.2 V, and 1.3 V VCCIO_PIO bank. The maximum input voltage driven into the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.
50 The VICM(DC) voltage must not exceed 1.2 V when on-chip differential termination (RD OCT) is disabled with the use of external on-board termination.