LVDS SERDES Specifications
DPA Lock Time Specifications
LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported
Memory Output Clock Jitter Specifications
Performance Specifications of the HBM2E Interface
Performance Specifications of Network on Chip (NoC)
NOC Reference Clock Requirements
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
I/O Standard | VIL(DC) (V) | VIH(DC) (V) | VIL(AC) (V) | VIH(AC) (V) |
---|---|---|---|---|
Maximum | Minimum | Maximum | Minimum | |
SSTL-12 | VREF – 0.075 | VREF + 0.075 | VREF – 0.100 | VREF + 0.100 |
HSTL-12 | VREF – 0.080 | VREF + 0.080 | VREF – 0.150 | VREF + 0.150 |
HSUL-12 | VREF – 0.100 | VREF + 0.100 | VREF – 0.135 | VREF + 0.135 |
POD12 | VREF – 0.055 | VREF + 0.055 | VREF – 0.070 | VREF + 0.070 |
POD11 | VREF – 0.055 | VREF + 0.055 | VREF – 0.070 | VREF + 0.070 |
Note: For output voltage swing calculation example, refer to the related information. Differential voltage referenced I/O standard uses two single-ended outputs with second output programmed as inverted.
Note: For eye height position estimation in EMIF interfaces, refer to the External Memory Interfaces Agilex™™ 7 M-Series FPGA IP User Guide. The eye mask estimation methodology defined in the External Memory Interfaces Agilex™™ 7 M-Series FPGA IP User Guide takes precedence over specifications in GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications table.