Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 9/05/2025
Public
Document Table of Contents

Table 28.  GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications For specification status, see the Data Sheet Status table
I/O Standard VIL(DC)  (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V)
Maximum Minimum Maximum Minimum
SSTL-12 VREF – 0.075 VREF + 0.075 VREF – 0.100 VREF + 0.100
HSTL-12 VREF – 0.080 VREF + 0.080 VREF – 0.150 VREF + 0.150
HSUL-12 VREF – 0.100 VREF + 0.100 VREF – 0.135 VREF + 0.135
POD12 VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070
POD11 VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070
Note: For output voltage swing calculation example, refer to the related information. Differential voltage referenced I/O standard uses two single-ended outputs with second output programmed as inverted.
Note: For eye height position estimation in EMIF interfaces, refer to the External Memory Interfaces Agilex™™ 7 M-Series FPGA IP User Guide. The eye mask estimation methodology defined in the External Memory Interfaces Agilex™™ 7 M-Series FPGA IP User Guide takes precedence over specifications in GPIO-B Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications table.