Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series

ID 769310
Date 4/01/2024
Document Table of Contents

GPIO-B Differential POD I/O Standards Specifications

Table 27.  GPIO-B Differential POD I/O Standards Specifications For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (%)43
Min Typ Max Max Min Max Min Max
POD1244 1.164 1.2 1.236 –0.11 0.11 –0.14 0.14 25
POD1144 1.067 1.1 1.133 –0.11 0.11 –0.14 0.14 25
43 Percentage of P-leg and N-leg crossing relative to the midpoint of P-leg and N-leg signal swings.
44 Each sub-bank can only support a single voltage tolerance. The VCCIO_PIO tolerance can be extended to ±5% if the entire GPIO-B sub-bank is operating in any of the following modes:
  • LVDS SERDES receiver mode with the use of 1.05 V, 1.1 V, 1.2 V True Differential Signaling input standard
  • PHYLITE mode
  • GPIO mode