Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.4. Partial Reconfiguration

The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform uses partial reconfiguration (PR) as a default mechanism to reconfigure the OpenCL kernel-related partition of the design without altering the static board interface that is in a running state.
Partial Reconfiguration Controller S10 (alt_pr) IP
Used to help support PR in this reference platform. During the PR process, the bitstream from host is transferred to this IP.
Partial Reconfiguration Region Controller (pr_region_controller_0) IP
Helps with the freeze and reset logic during the PR process. The interface of the pr_region.v is gated with the freeze signal from this IP to keep the static region in a known state during PR. For more information, refer to Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration.
Register (pr_base_id)
Stores the unique PR BASE ID that is generated on every base compile. During reprogramming of the device, this unique ID is used to identify the top compiles that are generated from the same base build. During the Intel® FPGA SDK for OpenCL™ Offline Compiler program flow, if the design being loaded and the existing design in the FPGA have the same PR BASE ID, then partial reconfiguration is used for reprogramming. Otherwise, full chip reprogramming is performed via JTAG interface.

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