Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform

Prior to designing an Intel® FPGA SDK for OpenCL™ Custom Platform, decide on design considerations that allow you to fully utilize the available hardware on your computing card.

The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform targets a subset of the hardware features available in the Intel® Stratix® 10 GX FPGA Development Kit.

Figure 4. Hardware Features of the Intel® Stratix® 10 GX FPGA Development Kit

Features of the s10_ref Reference Platform:

  • OpenCL Host

    The s10_ref Reference Platform uses a PCIe-based host that connects to the Intel® Stratix® 10 PCIe Gen3x8 hard IP core.

  • OpenCL Global Memory

    The hardware provides one 2-gigabyte (GB) DDR4 SDRAM daughtercard that is mounted on the HiLo connector and instantiated in the design using Intel® Stratix® 10 External Memory Interface IP (J14 in Hardware Features of the Intel® Stratix® 10 GX FPGA Development Kit).

  • FPGA Programming

    Via external cable and the Intel® Stratix® 10 GX FPGA Development Kit's on-board Intel® FPGA Download Cable II interface.

  • Guaranteed Timing

    The s10_ref Reference Platform relies on the Intel® Quartus® Prime Pro Edition compilation flow to provide guaranteed timing closure. The timing-clean s10_ref Reference Platform is preserved in the form of a precompiled post-fit netlist (that is, the base.qdb Intel® Quartus® Prime Database Export File). The Intel® FPGA SDK for OpenCL™ Offline Compiler imports this preserved post-fit netlist into each OpenCL kernel compilation.

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