Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Document Table of Contents

2.2.1. DDR4 IP Instantiation

The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform uses one DDR4 Controller IP to communicate with the physical memory.
Table 9.  DDR4 SDRAM Controller IP Configuration Highlights
Configuration Setting Description
Timing Parameters As per the computing card's data specifications.
Avalon Width Power of 2
EMIF S10 IP > Memory > DQ Width Currently, OpenCL™ does not support non-power-of-2 bus widths. As a result, the s10_ref Reference Platform uses the option that forces the DDR4 controller to power of 2. Use the additional pins of this x72 core for error checking between the memory controller and the physical module.
Byte Enable Support
EMIF S10 IP > Memory > Data Mask Enabled. Check the Data Mask option in the Memory tab of the EMIF Intel® Stratix® 10 IP.

Byte enable support is necessary in the core because the Intel® FPGA SDK for OpenCL™ requires byte-level granularity to all memories.

EMIF S10 IP > Controller > Enable Reordering Enabling the reordering of DDR4 memory accesses and a deeper command queue look-ahead depth might provide increased bandwidth for some OpenCL kernels. For a target application, adjust these and other parameters as necessary.
Note: Increasing the command queue look-ahead depth allows the DDR4 memory controller to reorder more memory accesses to increase efficiency, which improves overall memory throughput.
Debug Disabled for production.
Important: Follow limitations, such as no support for non-power of two bus widths and need for byte-level granularity, while designing your custom boards. Develop schematics to achieve byte-granularity by the external memory components used. Failure to do so may result in poor performance of your OpenCL applications.