Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Document Table of Contents

3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform

After you establish host communication and connect the external memory, test the FPGA programming process from kernel creation to program execution.
  1. Perform the steps outlined in INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/README.txt file to build the hardware configuration file from the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/ kernel source file.
    The environment variable INTELFPGAOCLSDKROOT points to the location of the Intel® FPGA SDK for OpenCL™ installation.
  2. Program your FPGA device with the hardware configuration file you created in step 1 and then restart your system.
  3. Remove the early-exit modification in the version_id_test function in the acl_pcie_device.cpp file that you implemented when you established communication between the board and the host interface.
    For Windows/Linux, the acl_pcie_device.cpp file is in the <your_custom_platform>\source\host\mmd folder.
  4. Recompile the MMD.
  5. Invoke the aocl diagnose <device_name> command, where <device_name> is the string you define in your Custom Platform to identify each board.
    In case you have only one variant, invoke the aocl diagnose acl0 command.
  6. Build the boardtest host application using the .sln file (Windows) or Makefile.linux (Linux) in the SDK's Custom Platform Toolkit.
    For Windows, the .sln file for Windows is in the INTELFPGAOCLSDKROOT\board\custom_platform_toolkit\tests\boardtest\host folder. For Linux, the Makefile.linux is in the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host directory.
  7. Set the environment variable CL_CONTEXT_COMPILER_MODE_INTELFPGA to a value of 3 and run the boardtest host application. The boardtest evaluates host to memory and kernel to memory connections. You may have to make modifications to boardtest host code base on your hardware design changes.
  8. Using the default compilation flow, test your custom platform file across several OpenCL design examples and confirm that the OpenCL design examples function correctly on the accelerator board.
    For more information about CL_CONTEXT_COMPILER_MODE_INTELFPGA, refer to Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues.