Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.7.1. Supply the Kernel Clock

In the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform, the OpenCL™ Kernel Clock Generator component provides the kernel clock and its 2x variant.

The REF_CLK_RATE parameter specifies the frequency of the reference clock that connects to the kernel PLL (kernel_pll_refclk). For the s10_ref Reference Platform, the REF_CLK_RATE frequency is 50 MHz.

The KERNEL_TARGET_CLOCK_RATE parameter specifies the frequency that the Intel® Quartus® Prime Pro Edition software attempts to achieve during compilation. The board hardware contains some logic that the kernel clock clocks. At a minimum, the board hardware includes the clock crossing hardware. To prevent this logic from limiting the fmax achievable by a kernel, the KERNEL_TARGET_CLOCK_RATE must be higher than the frequency that a simple kernel can achieve on your device. For the Intel® Stratix® 10 GX FPGA Development Kit that the s10_ref Reference Platform targets, the KERNEL_TARGET_CLOCK_RATE is 500 GHz.

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