Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.6.5. Pipelining

You must manually insert pipelines throughout the FPGA system.

In the Platform Designer, you can implement pipelines via an Avalon® -MM Pipeline Bridge component by setting the following pipelining parameters within the Avalon® MM Pipeline Bridge dialog box:

  • Select Pipeline command signals
  • Select Pipeline response signals
  • Select both Pipeline command signals and Pipeline response signals

Examples of Pipeline Implementation

  • Signals that traverse long distances because of the floorplan's shape or the region-to-region gaps require additional pipelines.

    The DMA at the bottom of the FPGA must connect to the DDR4 memory at the top of the FPGA. To achieve timing closure of the board interface logic at a DDR4 clock speed of 233 MHz, additional pipeline stages between the OpenCL™ Memory Bank Divider component and the DDR4 controller IP are necessary. In the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform's board.qsys Platform Designer system, the pipeline stages are named pipe_stage.

    The middle pipeline stage, kernel_ddra_bridge, combines both the direct kernel DDR4 accesses and the accesses through the OpenCL Memory Bank Divider. The multistage pipeline approach ensures that the kernel entry point to the pipeline is neither geared towards the OpenCL Memory Bank Divider, which is close to the PCIe* IP core, nor the DDR4 IP core, which is at the very top of the FPGA.

Did you find the information on this page useful?

Characters remaining:

Feedback Message