Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design

Modify the Intel® Quartus® Prime design for the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform to fit your design needs.

You can add a component in Platform Designer and connect it to the existing system, or add a Verilog file to the available system. After adding the custom components, connect those components in Platform Designer.

  1. Instantiate your PCIe controller, as described in Host-to- Intel® Stratix® 10 Communication over PCIe section.
  2. Instantiate any memory controllers and I/O channels. You can add the board interface hardware either as Platform Designer components in the board.qsys Platform Designer system or as HDL in the top.v file.
    The board.qsys file and the top.v file are in the <your_custom_platform>/hardware/<board_name> directory.
  3. Modify the device.tcl file to match all the correct settings for the device on your board. The device.tcl file is sourced into opencl_bsp_ip.qsf and flat.qsf files.
  4. Modify the <your_custom_platform>/hardware/<board_name>/flat.qsf file to change settings for your system. The base.qsf and top.qsf files will include all settings from the flat.qsf file.
    All .qsf files are in the <your_custom_platform>/hardware/<board_name> directory. Ensure that the flat.qsf file does not have any IP_FILE assignments after the assignment that adds top_post.sdc to the project since this changes the order in which SDC files are read during compile. Refer to Addition of Timing Constraints for more information about SDC ordering.

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