Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.6.6. DDR4 Calibration

The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform includes special mechanisms to ensure the functional stability of the Intel® Stratix® 10 silicon. For example, the DDR4 memory might not calibrate successfully after FPGA reconfiguration.

The driver within the s10_ref Reference Platform can detect a failed calibration via the Uniphy Status to AVS IP, and retrigger calibration through the ddr4_calibrate IP block.

The following two components in the mem.qsys design helps with the DDR calibration:
  • ACL Uniphy Status to AVS for A10 (uniphy_status_20nm): Helps to read the DDR status from the DDR IP.
  • ACL SW Reset (ddr4_calibrate): Issues reset to DDR IP.

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