Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Document Table of Contents

2.2.3. DDR4 Connection to the OpenCL Kernel

The OpenCL™ kernel needs to connect directly to the memory controller in the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform via a FIFO-based clock crosser.

A clock crosser is necessary because the kernel interface for the compiler must be clocked in the kernel clock domain. In addition, the width, address width, and burst size characteristics of the kernel interface must match those specified in the OpenCL Memory Bank Divider connecting to the host. Appropriate pipelining also exists between the clock crosser and the memory controller.

To get maximum kernel clock speed for Intel® Stratix® 10 devices, custom hyper-optimized CCB and AVMM Bridge are used in this path. The CCB is in mem.qsys and the bridge is stall-free that helps in fmax. The two end points, clock crosser and logic in the kernel supports AVMM stall latency.

Important: Ensure that the WAITREQUEST_ALLOWANCE in ACL hyper-optimized CCB matches that value in board_spec.xml for that interface. The reference design BSP has one ACL hyper-optimized bridge in the static region and one in the kernel generated logic. Hence, a WAITREQUEST_ALLOWANCE value of 6 is used. Intel recommends that you leave this number as is for best performance. If you have timing closure problems, add standard Platform Designer bridges after the ACL hyper-optimized CCB in the DDR clock domain. For an additional bridge that you add, add 2 to the WAITREQUEST_ALLOWANCE.

Did you find the information on this page useful?

Characters remaining:

Feedback Message