2.2.3. DDR4 Connection to the OpenCL Kernel
A clock crosser is necessary because the kernel interface for the compiler must be clocked in the kernel clock domain. In addition, the width, address width, and burst size characteristics of the kernel interface must match those specified in the OpenCL Memory Bank Divider connecting to the host. Appropriate pipelining also exists between the clock crosser and the memory controller.
To get maximum kernel clock speed for Intel® Stratix® 10 devices, custom hyper-optimized CCB and AVMM Bridge are used in this path. The CCB is in mem.qsys and the bridge is stall-free that helps in fmax. The two end points, clock crosser and logic in the kernel supports AVMM stall latency.
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