Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

3.9. Modifying the Kernel PLL Reference Clock

The Intel® Stratix® 10 GX FPGA Reference Platform uses an external 50 MHz clock as a reference for the I/O PLL. The I/O PLL relies on this reference clock to generate the internal kernel_clk clock, and the kernel_clk2x clock that runs at twice the frequency of kernel_clk.
When porting the s10_ref Reference Platform to your own board using a different reference clock, update the board.qsys and top.sdc files with the new reference clock speed.
  1. In the <your_custom_platform>/hardware/<board_name>/board.qsys file, update the REF_CLK_RATE parameter value on the kernel_clk_gen IP module.
  2. In the <your_custom_platform>/hardware/<board_name>/top.sdc file, update the create_clock assignment for config_clk in top.sdc.
  3. In the <your_custom_platform>/hardware/<board_name>/top.v file, update the comment for the config_clk input port, which is connected to kernel_pll_refclk in board.qsys.
After you update the board.qsys and the top.sdc files, the post_flow_pr.tcl script automatically determines the I/O PLL reference frequency and computes the correct PLL settings for your kernel.

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