Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues

Set Intel® FPGA SDK for OpenCL™ -specific environment variables to help diagnose Custom Platform design problems.
Table 10.   Intel® FPGA SDK for OpenCL™ -Specific Environment Variables for Identifying Custom Platform Design Problems
Environment Variable Description
ACL_HAL_DEBUG Set this variable to a value of 1 to 5 to enable increasing debug output from the Hardware Abstraction Layer (HAL), which interfaces directly with the MMD layer.
ACL_PCIE_DEBUG Set this variable to a value of 1 to 10000 to enable increasing debug output from the MMD. This variable setting is useful for confirming that the version ID register was read correctly and the UniPHY IP cores are calibrated.
ACL_PCIE_JTAG_CABLE Set this variable to override the default quartus_pgm argument that specifies the cable number. The default is cable 1. If there are multiple Intel® FPGA Download Cables, you can specify a particular one here.
ACL_PCIE_JTAG_DEVICE_INDEX Set this variable to override the default quartus_pgm argument that specifies the FPGA device index. By default, this variable has a value of 2. If the FPGA is not the first device in the JTAG chain, you can customize the value.
ACL_PCIE_USE_JTAG_PROGRAMMING Set this variable to force the MMD to reprogram the FPGA using the JTAG cable.
ACL_PCIE_DMA_USE_MSI Set this variable if you want to use MSI for DMA transfers on Windows.
CL_CONTEXT_COMPILER_MODE_INTELFPGA Unset this variable or set it to a value of 3. The OpenCL host runtime reprograms the FPGA as needed, which it does at least once during initialization. To prevent the host application from programming the FPGA, set this variable to a value of 3.

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