Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.1.5. Direct Memory Access

The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform relies on the PCIe* hard IP core's soft DMA engine to transfer data. The Intel® Stratix® 10 PCIe hard IP core's DMA interface is instantiated as a soft IP inside the PCIe hardware when the Avalon-MM with DMA application interface type is selected in the IP parameter editor.
Note: The DMA interface is capable of full duplex data transfers. However, the driver handles one read or write transfer at a time.

Hardware Considerations

The instantiation process exports the DMA controller agent ports (that is, rd_dts_agent and wr_dts_agent) and host ports (that is, rd_dcm_host and wr_dcm_host) into the PCIe module. Two additional host ports, dma_rd_host and dma_wr_host, are exported for DMA read and write operations, respectively. For the DMA interface to function properly, all these ports must be connected correctly in the board.qsys Platform Designer system, where the PCIe hard IP is instantiated.

At the start of DMA transfer, the DMA Descriptor Controller reads from the DMA descriptor table in user memory, and stores the status and the descriptor table into a FIFO address. There are two FIFO addresses: Read Descriptor FIFO address and Write Descriptor FIFO address. After storing the descriptor table into a FIFO address, DMA transfers into the FIFO address can occur. The dma_rd_host port, which moves data from user memory to the device, must connect to the rd_dts_agent and wr_dts_agent ports. Because the dma_rd_host port connects to DDR4 memory also, the locations of the rd_dts_agent and wr_dts_agent ports in the address space must be defined in the hw_pcie_dma.h file.

The rd_dcm_host and wr_dcm_host ports must connect to the txs port. At the end of the DMA transfer, the DMA controller writes the MSI data and the done status into the user memory via the txs agent. The txs agent is part of the PCIe* hard IP in board.qsys.

All modules that use DMA must connect to the dma_rd_host and dma_wr_host ports. For DDR4 memory connection, Intel® recommends implementing an additional pipeline to connect the two 256-bit PCIe DMA ports to the 512-bit memory agent. For more information, refer to the DDR4 Connection to PCIe* Host section.

Software Considerations

The MMD layer uses DMA to transfer data if it receives a data transfer request that satisfies both of the following conditions:

  • A transfer size that is greater than 1024 bytes
  • The starting addresses for both the host buffer and the device offset are aligned to 64 bytes

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