Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform

Calibrate the external memory IP and controllers in your Custom Platform, and connect them to the host.
  1. In your Custom Platform, instantiate your external memory IP based on the information in the DDR4 as Global Memory for OpenCL Applications section. Update the information pertaining to the global_mem element in the <your_custom_platform>/hardware/<board_name>/board_spec.xml file.
  2. Remove the boardtest hardware configuration file (that is, aocx) that you created during the integration of your Custom Platform with the Intel® FPGA SDK for OpenCL™ .
  3. Recompile the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl kernel source file.
    The environment variable INTELFPGAOCLSDKROOT points to the location of the SDK installation.
  4. Reprogram the FPGA with the new boardtest hardware configuration file and then restart your system.
  5. Modify the wait_for_uniphy function in the acl_pcie_device.cpp MMD source code file to exit after checking the UniPHY status register. Rebuild the MMD software.
    For Windows/Linux, the acl_pcie_device.cpp file is in the <your_custom_platform>\source\host\mmd folder.
  6. Run the aocl diagnose SDK utility and confirm that the host reads back both the version ID and the value 0 from the uniphy_status component.
    The utility should return the message Uniphy are calibrated.
  7. Consider analyzing your design in the Signal Tap logic analyzer to confirm the successful calibration of all memory controllers.
    Note: For more information on Signal Tap logic analyzer, download the Signal Tap II Logic Analyzer tutorial from the University Program Tutorial page.

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