Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide
ID
683809
Date
3/28/2022
Public
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe®
2.2. DDR4 as Global Memory for OpenCL Applications
2.3. Host Connection to OpenCL Kernels
2.4. Partial Reconfiguration
2.5. Other Components in the Reference Design
2.6. Intel® Stratix® 10 FPGA System Design
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows
2.9. Addition of Timing Constraints
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™
2.11. Intel® Stratix® 10 FPGA Programming Flow
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities
2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access
2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP
2.1.3. Instantiation of the version_id Component
2.1.4. Board Support Package Software Layer
2.1.5. Direct Memory Access
2.1.6. Message Signaled Interrupt
2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
3.1. Initializing Your Intel® Stratix® 10 Custom Platform
3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design
3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™
3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment
3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication
3.6. Branding Your Intel® Stratix® 10 Custom Platform
3.7. Changing the Device Part Number
3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform
3.9. Modifying the Kernel PLL Reference Clock
3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform
3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
2.2. DDR4 as Global Memory for OpenCL Applications
The Intel® Stratix® 10 GX FPGA Development Kit has one bank of 2GB x72 DDR4-1866 SDRAM. The DDR4 SDRAM is a daughtercard that is mounted to the development kit's HiLo connector.
In the current version of the s10_ref Reference Platform, all Platform Designer components related to the DDR4 global memory are now part of the INTELFPGAOCLSDKROOT/board/s10_ref/hardware/s10gx/mem.qsys Platform Designer subsystem within board.qsys.
Dependencies
DDR4 external memory interfaces
For more information about the DDR4 external memory interface IP, refer to the DDR3 Board Design Guidelines and DDR4 Board Design Guidelines sections in Intel Stratix 10 External Memory Interfaces IP User Guide.
To use the DDR4 SDRAM as global memory for Intel® FPGA SDK for OpenCL™ designs, you must instantiate the memory controller IP, connect the memory IP to the host, and connect the memory IP to the kernel.