Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Document Table of Contents

2.2. DDR4 as Global Memory for OpenCL Applications

The Intel® Stratix® 10 GX FPGA Development Kit has one bank of 2GB x72 DDR4-1866 SDRAM. The DDR4 SDRAM is a daughtercard that is mounted to the development kit's HiLo connector.

In the current version of the s10_ref Reference Platform, all Platform Designer components related to the DDR4 global memory are now part of the INTELFPGAOCLSDKROOT/board/s10_ref/hardware/s10gx/mem.qsys Platform Designer subsystem within board.qsys.


DDR4 external memory interfaces

For more information about the DDR4 external memory interface IP, refer to the DDR3 Board Design Guidelines and DDR4 Board Design Guidelines sections in Intel Stratix 10 External Memory Interfaces IP User Guide.

To use the DDR4 SDRAM as global memory for Intel® FPGA SDK for OpenCL™ designs, you must instantiate the memory controller IP, connect the memory IP to the host, and connect the memory IP to the kernel.