Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.8.1. Compile Flow

Following are the types of compile flows:

Flat Compile
A flat revision uses the flat.qsf settings file and performs a flat compilation of the entire design (BSP along with kernel generated hardware). The flat.qsf has minimal location constraints, and generally has all of the pin assignments (sourced using device.tcl) and basic settings to compile a hardware design. To compile a flat revision of your BSP, use -bsp-flow=flat modifier option with the aoc command.
Base Compile
A base revision uses the base.qsf settings file to compile the board support package. The base.qsf uses all the flat.qsf settings and adds the required location constraints and Logic Lock regions on top of it. The kernel clock target is relaxed during the base compilation so that the BSP hardware has more freedom to meet timing. A base.qar database is created to preserve the BSP hardware, which is the static region. The revision can be compiled using -bsp-flow=base modifier option with the aoc command.
Top Compile
The top flow, also known as the import compile, is generally the default flow of kernel compiles. It uses the top.qsf settings file for compilation and the base.qar from a base revision compile to import the pre-compiled netlist of the static region. It guarantees the timing closed static region and compiles only the kernel generated hardware. It also increases the kernel clock target to obtain the best kernel maximum operating frequency (fmax).

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