Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Document Table of Contents

2.6.2. Resets

The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform design includes the implementation of reset drivers.

These reset drivers include:

  • The por_reset_counter in the INTELFPGAOCLSDKROOT/board/s10_ref/hardware/s10gx/board.qsys Platform Designer system implements the power-on-reset. The power-on-reset resets all the hardware on the device by issuing a reset for a number of cycles after the FPGA completes configuration.
  • The PCIe® bus issues a perst reset that resets all hardware on the device.
  • The OpenCL™ Kernel Interface component issues the kernel_reset that resets all logic in the kernel clock domain.

The power-on-reset and the perst reset are combined into a single global_reset; therefore, there are only two reset sources in the system (that is, global_reset and kernel_reset). However, these resets are explicitly synchronized across the various clock domains, resulting in several reset interfaces.

Important Considerations Regarding Resets

  • Synchronizing resets to different clock domains might cause several high fan-out resets.

    Platform Designer automatically synchronizes resets to the clock domain of each connected component. In doing so, the Platform Designer instantiates new reset controllers with derived names that might change when the design changes. This name change makes it difficult to make and maintain global clock assignments to some of the resets. As a result, for each clock domain, there are explicit reset controllers. For example, global_reset drives reset_controller_pcie and reset_controller_ddr4. However, they are synchronized to the PCIe and DDR4 clock domains, respectively.

  • Resets and clocks must work together to propagate reset to all logic.

    Resetting a circuit in a given clock domain involves asserting the reset over a number of clock cycles. However, your design may apply resets to the PLLs that generate the clocks for a given clock domain. This means a clock domain can hold in reset without receiving the clock edge that is necessary for synchronous resets. In addition, a clock holding in reset might prevent the propagation of a reset signal because it is synchronized to and from that clock domain. Avoid such situations by ensuring that your design satisfies the following criteria:

    • Generate the global_reset signal off the free-running config_clk.
    • The ddr4_calibrate IP resets the External Memory Interface controller separately.

  • Apply resets to both reset interfaces of a clock-crossing bridge or FIFO component.

    FIFO content corruption might occur if only part of a clock-crossing bridge or a dual-clock FIFO component is reset. These components typically provide a reset input for each clock domain; therefore, reset both interfaces or none at all. For example, in the s10_ref Reference Platform, kernel_reset resets all the kernel clock-crossing bridges between DDR on both the m0_reset and s0_reset interfaces.