Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Document Table of Contents

2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature

While using the Intel® FPGA SDK for OpenCL™ Offline Compiler program flow, the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform automatically tries to detect the cable by default when programming the FPGA via the Intel FPGA Download Cable. This flow is useful when loading a new base image to the FPGA, where partial reconfiguration cannot be used.

You can set the ACL_PCIE_JTAG_CABLE or ACL_PCIE_JTAG_DEVICE_INDEX environment variables to disable the auto-detect feature and use values that you define.

Cable autodetect is useful when you have multiple devices connected to a single host.

The memory-mapped device (MMD) uses in-system sources and probes to identify the cable connected to the target board. You must instantiate the board_cade_id_0 register block and connect it to Bar 4 with the correct address map. You must also instantiate board_in_system_sources_probes_0, which is an in-system sources and probe component, and connect it to board_cade_id_0 register.

The MMD must be updated to take in the relevant changes. Add the scripts/find_jtag_cable.tcl script to your custom platform.

When the FPGA is being programmed via the Intel FPGA Download Cable, the MMD invokes quartus_stp to execute the find_jtag_cable.tcl script. The script identifies the cable and index number which is then used to program the FPGA through the quartus_pgm command.