Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Document Table of Contents

2.9. Addition of Timing Constraints

A Custom Platform must apply the correct timing constraints to the Intel® Quartus® Prime project. In the Intel® Stratix® 10 FPGA Development Kit Reference Platform, the top.sdc file contains all timing constraints applicable before IP instantiation in Platform Designer. The top_post.sdc file contains timing constraints applicable after Platform Designer generation is run.

The order of the application of time constraints is based on the order of appearance of the top.sdc and top_post.sdc files in the flat.qsf file. To ensure proper SDC ordering, the opencl_bsp_ip.qsf file is sourced between top.sdc and top_post.sdc files. All IPs are added to opencl_bsp_ip.qsf during aoc compile flow. This ensures that the SDC order is top.sdc followed by SDCs for the IP components and then top_post.sdc in all aoc compiles.

An important constraint in the s10_ref Reference Platform is the multicycle constraint for the kernel reset in the top_post.sdc file. Using global routing saves routing resources and provides more balanced skew. However, the delay across the global route might cause recovery timing issues that limit kernel clock speed. Therefore, it is necessary to include a multicycle path on the global reset signal.
#Make the kernel reset multicycle
#changes made to the multicycle path here need to also be reflected in the 
#multicycle value in scripts/adjust_plls_s10.tcl
Set_multicycle_path -to * -setup 15 -from {freeze_wrapper_inst|board_kernel_reset_n_reg}
Set_multicycle_path -to * -hold 14 -from {freeze_wrapper_isnt|board_kernel_reset_reset_n_reg}