ID 683809
Date 3/28/2022
Public

## 2.1.4.1. Common Hardware Constants in Software Headers Files

After you build the PCIe component in your hardware design, you need a software layer to communicate with the board via PCIe. To enable communication between the board and the host interface, define the hardware constants for the software in header files.

The two header files that describe the hardware design to the software are in the following locations:

• For Windows systems, the header files are in the INTELFPGAOCLSDKROOT\board\s10_ref\source\include folder, where INTELFPGAOCLSDKROOT is the path to the SDK installation.
• For Linux systems, the header files are in the INTELFPGAOCLSDKROOT/board/s10_ref/linux64/driver directory.
Important: Ensure that hw_pcie_constants.h and hw_pcie_dma.h header files match the MMD offsets in the address map of board.qsys. Use the Address Map viewer in Platform Designer to view the PCIe BAR4 offsets and match this information with hw_pcie_constants.h file as shown in the following image. Refer to the following table for more information on hw_pcie_dma.h.
Figure 7. Address Map for board.qsys from s10_ref Reference Platform

Following is a snapshot from INTELFPGAOCLSDKROOT/board/s10_ref/linux64/driver/hw_pcie_constants.h

//Version ID and Uniphy Status
#define ACL_VERSIONID_BAR                    4
#define ACL_VERSIONID_OFFSET            0xcfc0
Table 7.   Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Header Files
hw_pcie_constants.h

Header file that defines most of the hardware constants for the board design specially in board.qsys.

This file includes constants such as the IDs described in PCIe Device Identification Registers, BAR number, and offset for different components in your design. In addition, this header file also defines the name strings of ACL_BOARD_PKG_NAME, ACL_VENDOR_NAME, and ACL_BOARD_NAME.

Update the information in this file whenever you change the board design.

hw_pcie_dma.h

Header file that defines DMA-related hardware constants.

• ACL_PCIE_DMA_ONCHIP_RD_FIFO_BASE refers to the Platform Designer address of rd_dts_agent on the PCIe IP's dma_rd_host.
• ACL_PCIE_DMA_ONCHIP_WR_FIFO_BASE refers to the Platform Designer address of wr_dts_agent on the PCIe IP's dma_rd_host.

Update these addresses whenever you change the board design. Refer to the Direct Memory Access section for more information.

• ACL_PCIE_DMA_TABLE_SIZE refers to the DMA descriptor FIFO depth connected to the DMA. When using the internal descriptor controller, refer to the DMA Descriptor Controller Registers section in the Intel® Stratix® 10 Avalon-MM DMA Interface for PCIe Solutions User Guide for the required size.
• ACL_PCIE_DMA_PAGES_LOCKED specifies the maximum pages you can lock. You may modify this constant to improve performance.
• ACL_PCIE_DMA_NON_ALIGNED_TRANS_LOG specifies the starting and ending power-of-two values that non-aligned DMA transfers should have. You may modify this constant to improve performance.