2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP
|ID Register Name||ID Provider||Description||Parameter Name in PCIe IP Core|
|Vendor ID||PCI-SIG®||Identifies the FPGA manufacturer.
Always set this register to 0x1172, which is the Intel® vendor ID.
|Device ID||Intel®||Describes the PCIe configuration on the FPGA according to Intel® 's internal guideline.
Set the device ID to the device code of the FPGA on your accelerator board.
For the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform, set the Device ID register to 0x5170, which signifies Gen 3 speed, 8 lanes, Intel® Stratix® 10 device family, and Avalon® -MM interface, respectively.
Refer to Intel® FPGA SDK for OpenCL™ 's Numbering Convention for PCIe* Hard IP Device ID table for more information.
|Revision ID||When setting this ID, ensure that it matches the following revision IDs:
The Intel® FPGA SDK for OpenCL™ utility checks the base class value to verify whether the board is an OpenCL™ device.
Do not modify the class code settings.
|Subsystem Vendor ID||Board vendor||Identifies the manufacturer of the accelerator board.
Set this register to the vendor ID of manufacturer of your accelerator board. For the s10_ref Reference Platform, the subsystem vendor ID is 0x1172.
If you are a board vendor, set this register to your vendor ID.
|Subsystem Vendor ID|
|Subsystem Device ID||Board vendor||Identifies the accelerator board.
The SDK uses this ID to identify the board because the software might perform differently on different boards. If you create a Custom Platform that supports multiple boards, use this ID to distinguish between the boards. Alternatively, if you have multiple Custom Platforms, each supporting a single board, you can use this ID to distinguish between the Custom Platforms.
Important: Make this ID unique to your Custom Platform. For example, for the s10_ref Reference Platform, the ID is 0x5170.
|Subsystem Device ID|
The kernel driver uses the Vendor ID, Subsystem Vendor ID and the Subsystem Device ID to identify the boards it supports. The SDK's programming flow checks the Device ID to ensure that it programs a device with a .aocx Intel® FPGA SDK for OpenCL™ Offline Compiler executable file targeting that specific device.
|Location in ID||Definition|
|10:8||Number of lanes
|3||1 — Soft IP (SIP)
This ID indicates that the PCIe protocol stack is implemented in soft logic. If unspecified, the IP is considered a hard IP.
|2:0|| Platform Designer PCIe interface type
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