Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design

One of the key features of the Intel® FPGA SDK for OpenCL™ is that it abstracts away hardware details, such as timing closure, for software developers.

Both the SDK and the BSP contribute to the implementation of the SDK's guaranteed timing closure feature.

The SDK provides the IP to generate the kernel clock, and a post-flow script that ensures this clock is configured with a safe operating frequency confirmed by timing analysis. The SDK imports a post-fit netlist during a top compile that has already achieved timing closure on all non-kernel clocks.

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